1. Field of the Invention
The present invention relates to a semiconductor memory and a semiconductor device.
2. Description of the Prior Art
Recently, a nonvolatile semiconductor memory such as an EPROM (erasable and programmable read only memory) or an EEPROM (electrically erasable and programmable read only memory) is watched with interest as a semiconductor memory capable of substituting for a magnetic memory such as a hard disk or a floppy disk.
Each memory cell of an EPROM or an EEPROM stores carriers in a floating gate electrode for storing data in response to presence/absence of carriers and reading data by detecting change of a threshold voltage responsive to presence/absence of carriers. In particular, the EEPROM includes a flash EEPROM erasing data on the overall memory cell array or dividing the memory cell array into arbitrary blocks for erasing data in units of the blocks. The flash EEPROM, referred to also as a flash memory, is capable of attaining a high capacity, low power consumption and a high-speed operation and excellent in shock resistance, and hence applied to various types of portable devices. Further, the flash EEPROM having memory cells can be readily integrated as compared with the EEPROM.
In general, a stacked gate memory cell and a split gate memory cell are proposed as those forming a flash EEPROM.
In the stacked gate memory cell, electrons in a channel of a semiconductor substrate are converted to hot electrons and injected into a floating gate electrode in writing for storing electrons in the floating gate electrode. At this time, a voltage of ten-odd V must be applied to a control gate electrode. In erasing for extracting electrons stored in the floating gate electrode of the stacked gate memory cell, a Fowler-Nordheim tunnel current (hereinafter referred to as an F-N tunnel current) is fed from a source region to the floating gate electrode. At this time, a voltage of ten-odd V must be applied to the source region.
In the split gate memory cell, electrons in a channel of a semiconductor substrate are converted to hot electrons and injected into a floating gate electrode in writing for storing electrons in the floating gate electrode. At this time, a voltage of about ten V must be applied to a source region. In erasing for extracting electrons from the floating gate electrode of the split gate memory cell, an F-N tunnel current is fed from a control gate electrode to the floating gate electrode. At this time, a voltage of about ten V must be applied to the control gate electrode.
Thus, each of the conventional stacked gate memory cell and the conventional split gate memory cell utilizes hot electrons for injecting electrons into the floating gate electrode in writing while utilizing an F-N tunnel current for extracting the electrons stored in the floating gate electrode in erasing.
In order to maintain carriers stored in the floating gate electrode over a long period, an insulator film enclosing the floating gate electrode must be increased in thickness. However, electrons are injected into or extracted from the floating gate electrode through hot electrons or an F-N current. As the thickness of the insulator film enclosing the floating gate electrode is increased, therefore, the voltage (hereinafter referred to as an operating voltage of the memory cell) applied to the control gate electrode or the drain region in writing or erasing must be increased.
The operating voltage of the memory cell is generated in a step-up circuit. In this case, the upper limit of practically generable voltages is ten-odd V. When a silicon oxide film is employed as the insulator film enclosing the floating gate electrode, the thickness of this silicon oxide film cannot exceed 8 to 10 nm if the operating voltage of the memory cell is ten-odd V. In general, therefore, the thickness of a silicon oxide film employed as the insulator film enclosing the floating gate electrode is set to 8 to 10 nm, in order to suppress the operating voltage of the memory cell to ten-odd V. When the thickness of the silicon oxide film is about 8 to 10 nm, electrons stored in the floating gate electrode can be maintained for a period (about 10 years) satisfactory to some extent.
Also when holes are stored in the floating gate electrode, the thickness of the silicon oxide film employed as the insulator film enclosing the floating gate electrode is set to 8 to 10 nm similarly to the aforementioned case of storing electrons, for suppressing the operating voltage of the memory cell to ten-odd V and maintaining the holes stored in the floating gate electrode for a period satisfactory to some extent.
The recent flash EEPROM, increased in life by increasing the period for maintaining the carriers stored in the floating gate electrode, is required to attain a lower voltage, an operation at a higher speed, lower power consumption and a higher degree of integration.
As hereinabove described, the thickness of the silicon oxide film employed as the insulator film enclosing the floating gate electrode is generally set to 8 to 10 nm. In order to increase the life of the flash EEPROM, therefore, the thickness of the silicon oxide film must not be reduced beyond 8 nm.
When the operating voltage of the memory cell is reduced, the time (lead time) for stepping up the voltage is so reduced that writing and erasing can be performed at a high speed. Further, power consumption can be reduced. In most frequently performed reading, a low-voltage operation and a large reading cell current are extremely advantageous for high-speed reading.
The scale of the step-up circuit for generating the operating voltage of the memory cell is increased as the generated voltage is increased. The occupied area (transistor size) of a transistor forming a peripheral circuit (a decoder, a sense amplifier, a buffer or the like) of the flash EEPROM is increased on the substrate as the withstand voltage is increased. When the operating voltage of the memory cell s reduced, therefore, the scale of the step-up circuit as well as the size of the transistor forming the peripheral circuit are reduced and hence a higher degree of integration can be attained.
Therefore, all of a high-speed operation, low power consumption and a high degree of integration can be simultaneously implemented by reducing the operating voltage o the memory cell.
In each of the conventional stacked gate memory cell and the conventional split gate memory cell, however, electrons are injected into or extracted from the floating gate electrode through hot electrons or an F-N tunnel current. When a silicon oxide film is employed as the insulator film enclosing the floating gate electrode, therefore, it is difficult to reduce the operating voltage of the memory cell below the present level while maintaining the thickness of the silicon oxide film at the present level of 8 to 10 nm. In other words, it is difficult to reduce the operating voltage of the memory cell while maintaining a life equivalent to the present level unless the structure of the conventional stacked gate or split gate memory cell is changed.